Core speed is the multiplication result, per core
Multiplier CPU dynamically adjust clock speed
Bus Speed Base clock frequency from the Quartz crystal
L1 Cache is In two parts, Instruction and Data. Both are 32 KBytes in size
L2 Cache as expected is larger at 256 Bytes
L3 Cache Finally, L3 is 6M bytes
DRAM:Frequency Speed of the memory bus
FSB:DRAM Base clock /3 * up to get DRAM Frequency
Column Address Strobe (CAS) latency, or CL, is the delay in clock cycles between the READ command and the moment data is available. Smaller the number the better